The approaches described in this section could be pursued, but are not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
Modern Integrated Circuits (ICs), for instance ICs used in mobile devices, require a high operating frequency as well as a low current leakage in standby mode, which leads to intensive usage of a power gating techniques. Power gating is a technique that uses low-leakage MOS transistors, also called sleep transistors, as switches to shut off the power supply to internal circuitry parts of an IC in standby or sleep mode, to reduce the stand-by and/or leakage power of the IC. Implementation of power gating relies on an on-chip power switch arranged between the supply voltage source and the power gated circuitry, which creates an additional voltage drop.
Increasing the voltage of the voltage source cannot be considered as a solution for compensating for the voltage drop, since at low current, the voltage drop would tend to zero and the junction voltage may thus become higher than the maximum voltage allowed by the manufacturing process of the functional blocks in the power gated domain.
The power switch needs therefore to be large in order to minimize this voltage drop, since large gate transistors offer smaller impedance and thus lower voltage drop for a given current flowing through the switch. This, however, has a significant die area impact, and also increases leakage through the switch itself. Hence, the IC designer must find a balance between minimizing the voltage drop, and increasing the die area and leakage on the power gating switch.
US patent application publication 2006/0244512 A1 to ATI Technologies Inc. discloses an apparatus and method for matching voltages between two or more circuits within an integrated circuit. The apparatus includes a comparator circuit, comparing supply voltages to first and second circuits. The comparator outputs a variable error voltage based on the comparison, the error voltage relating to the difference in voltages. The error voltage is supplied to a variable current control circuit that variably sinks one of the supply voltages to a common potential in order to increase the IR drop in the circuit supplying voltage to one of the first and second circuits, thereby affording voltage adjustment in order to match the first and second circuits. Such voltage adjustment technique is however not optimal for mobile IC's.
US patent application 2008/0111534 A1 to Intel Inc. discloses a voltage regulator architecture for an integrated circuit. The described apparatus comprise a power switch array having multiple pass transistors, a voltage regulator array having multiple voltage regulators each coupled to a subset of the pass transistors, a subsystem circuit array having multiple subsystem circuits each coupled to a subset of the pass transistors, and a power management control unit coupled to the pass transistors and the voltage regulators. The power management control unit may be arranged to control the pass transistors and voltage regulators to provide different amounts of power to the subsystem circuits.
One could also consider changing the voltage level on the gate of the power switch transistor, like in analog gate-biasing techniques, but implementing such a technique for keeping the voltage drop constant over all the current variation range proves to be very difficult in practice.